刘雷波，清华大学集成电路学院长聘教授、博士生导师，教育部国家重大人才计划特聘教授，北京市优秀研究生导师，国家级一流本科课程负责人。

1999年和2004年分别在清华电子工程系和微电子所获得学士和博士学位。2004年留在清华大学任教，2006年~2017年分别在欧洲微电子中心、麻省理工学院、林肯大学、牛津大学进修与访问。长期从事软件定义芯片、硬件安全和密码芯片、VLSI数字信号处理等研究工作。发表高水平论文400余篇、授权发明专利200余项（美国专利20余项）、撰写著作10部、参与制定国家标准1项。先后担任国际权威期刊《IEEE Circuits and Systems Magazine》副主编、中国工程院院刊《信息与电子工程前沿》执行副主编；密码硬件顶级会议CHES、集成电路设计顶级会议ISSCC，及电子设计自动化顶级会议DAC的TPC委员，集成电路设计一流会议A-SSCC的管委会委员和大会主席等；中国密码学会密码芯片专委会副主任委员；ISO/IECJTC1/SC27国际标准注册专家。

刘雷波积极推动成果转化与技术应用，关键技术在一系列国家重大工程中取得批量应用。获国家技术发明二等奖、中国专利金奖、教育部技术发明一等奖、中国电子学会技术发明一等奖、英特尔中国学术成就奖-卓越合作奖等奖励，此外，美国微软公司在其官网对其个人技术贡献致谢。

刘雷波主持4门课，获首批国家级一流本科课程、清华大学本科生精品课、北京市青年教师教学竞赛一等奖、清华大学青年教师教学竞赛一等奖、清华大学青年教师教学优胜奖、MOOC教学先锋奖等多个教学奖励，所负责的大规模网络开放课程（MOOC）入选首批教育部高校在线教学国际平台，获清华大学“良师益友”称号。

Dr. Leibo Liu is a tenured professor at the School of Integrated Circuits, Tsinghua University. He is a Distinguished Professor under the National Major Talent Program of the Ministry of Education, an Outstanding Graduate Supervisor in Beijing, and the lead instructor of a National First-Class Undergraduate Course.

He earned his bachelor’s degree from the Department of Electronic Engineering in 1999 and his Ph.D. from the Institute of Microelectronics in 2004, both at Tsinghua University. After completing his Ph.D., he joined Tsinghua University as an assistant professor in 2004. From 2006 to 2017, he conducted research and visited several institutions, including IMEC (Interuniversity Microelectronics Centre) in Europe, the Massachusetts Institute of Technology, the University of Lincoln, and the University of Oxford.

His research focuses on mainly in twofold. First, Reconfigurable Computing and Software-Defined Chips. It includes the design architectures and compiling techniques for Software-Defined Chips and Reconfigurable Computing Processors (RCP), including applications in scientific computing, baseband DSP ICs, and AI computing. Second, Hardware Security and Trusted ICs. He developed reconfigurable cryptographic chips with built-in physical security enhancements and silicon-level primitives like PUF and TRNG Chips.  He has published over 400 peer-reviewed papers, holds more than 200 authorized invention patents (including over 20 U.S. patents), authored 10 books, and contributed to the formulation of one national standard.

He has served as an Associate Editor for the IEEE Circuits and Systems Magazine and as the Executive Deputy Editor-in-Chief of the Chinese Academy of Engineering Journal Frontiers of Information and Electronic Engineering. He has also been a TPC member for ISSCC (International Solid-State Circuits Conference), CHES (Cryptographic Hardware and Embedded Systems), and DAC (Design Automation Conference). He served as a committee member and conference chair for A-SSCC (Asian Solid-State Circuits Conference). Additionally, he is a Deputy Director of the Cryptographic Chip Committee of the Chinese Association for Cryptologic Research and a registered expert for ISO/IEC JTC 1/SC 27 international standards.

Dr. Liu actively promotes the transformation and application of research outcomes, with key technologies being deployed in a series of major national projects. He has received numerous awards, including the National Technology Invention Award (Second Class), the China Patent Gold Award, the Ministry of Education Technology Invention Award (First Class), the China Institute of Electronics Technology Invention Award (First Class), and the Intel China Academic Achievement Award for Outstanding Collaboration. Notably, Microsoft Corporation has publicly acknowledged his technical contributions on its official website.

Dr. Liu is known for his teaching. He has received numerous teaching awards, including the National First-Class Undergraduate Course (Inaugural Batch), Tsinghua University's Excellent Undergraduate Course, First Prize in the Beijing Young Teachers' Teaching Competition, First Prize in the Tsinghua University Young Teachers' Teaching Competition, the Tsinghua University Young Teachers' Teaching Excellence Award, and the Massive Open Online Course (MOOC) Teaching Pioneer Award. In addition, the Massive Open Online Course (MOOC) under his direction was selected for the Ministry of Education's first batch of International Platforms for Higher Education Online Teaching. Dr. Liu is the recipient of "Mentor and Friend" (Liang Shi Yi You) at Tsinghua University.

ORCID：https://orcid.org/0000-0001-7548-4116

Google Scholar：https://scholar.google.com/citations?user=fw9eAF0AAAAJ&hl=zh-CN

Some Representative Papers：

Note: Supervised students are indicated with an underline “_”.

Corresponding authors are indicated with an asterisk “*”.

1. C. Zhao, H. Shui, B. Yang, W. Zhu, Y. Cao, Z. Hou, Y. Liu, X. Han, S. Yin, W. Chen, H. Wang, J. Yang, M. Zhu, A. Zhang, Leibo Liu*. “A 17%/27% Area-/Energy-Overhead Glitch-Transition Secure SHA-3 Engine Fusing Dual-Rail Precharge Logic and Asymmetric Masking”, 2026 IEEE International Solid-State Circuits Conference (ISSCC). [Highlight Paper], Accepted

2. Y. Huang, H. Kong, I. Y. Chou, B. Wang, X. Kong, J. Zhu, L. Li, X. Li, H. Wang, A. Zhang, Leibo Liu. “SharpSAT: A Heuristic-Learning-Based SAT Accelerator Achieving 0.8μs/16.1μs Solution Time in SAT/UNSAT Cases”, 2026 IEEE International Solid-State Circuits Conference (ISSCC). Accepted.

3. X. Chen, B. Yang, W. Zhu, H. Wang, J. Yang, M. Zhu, A. Zhang, Leibo Liu*. “SiWB: A 28nm 800MHz 4.2-to-14.2Gbps/W Configurable Multi-core Architecture for White-box Block Cipher with Area-efficient Random Linear Transformation and Load-aware Inter-core Scheduling”, IEEE Journal of Solid-State Circuits (JSSC). Accepted

4. S. Lu, W. Zhu, B. Yang, J. Yang, Dai T., C. Chen, ... & Leibo Liu*. “HUTAO: A Reconfigurable Homomorphic Processing Unit with Cache Aware Operation Scheduling" for publication in the Journal of Solid State Circuits.”, IEEE Journal of Solid-State Circuits (JSSC). Accepted

5. Y. Zhang, J. Zhu, L. Li, … & Leibo Liu*. “A 28-nm 239-bp/μJ Agile Pangenome Analysis Accelerator for Multi-Scheme Read Mapping”. IEEE Journal of Solid-State Circuits (JSSC). 2025.

6. J. Zhu, B. Yang, L. Chen, J. Chen, Y. Zhang, ... & Leibo Liu*. “A 28-nm Software-Defined Accelerator Chip With Circuit-Pipeline Scaling and Intrinsic Physical Unclonable Function Enabling Secure Configuration”. IEEE Journal of Solid-State Circuits (JSSC). 2025

7. Y. Zhu, W. Zhu, Y. Ouyang, J. Sun, Q. Zhao, M. Zhu, ... Leibo Liu*. “PQPU: A 4.4-$\mu $ J/Op 69.4-kOPS Agile Post-Quantum Crypto-Processor Across Multiple Mathematical Problems”, IEEE Journal of Solid-State Circuits (JSSC), 60(6) (2025): 2261 -2275

8. S. Lu, W. Zhu, B. Yang, J. Yang, Dai T., C. Chen, ... & Leibo Liu*. “17.2 A 28nm 4.05 µJ/Encryption 8.72 kHMul/s Reconfigurable Multi-Scheme Fully Homomorphic Encryption Processor for Encrypted Client-Server Computing”. 2025 IEEE International Solid-State Circuits Conference (ISSCC). [Highlight Paper], IEEE, 2025, 68: 01-03.

9. Yihong Zhu, Wenping Zhu, Yi Ouyang, Junwen Sun, Min Zhu, Qi Zhao, Jinjiang Yang, Chen Chen, Qichao Tao, Guang Yang, Aoyang Zhang, Shaojun Wei, Leibo Liu*. “16.2 A 28nm 69.4 kOPS 4.4 μJ/Op Versatile Post-Quantum Crypto-Processor Across Multiple Mathematical Problems”, 2024 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA. 67: 298-300

10. D. Chen, T. Zhang, Y. Huang, J. Zhu, Y. Liu, P. Gou, ... Leibo Liu*. “Orinoco: Ordered Issue and Unordered Commit with Non-Collapsible Queues”. 2023 the 50th Annual International Symposium on Computer Architecture (ISCA), pp. 1-14.

11. X. Kong, Y. Huang, J. Zhu, X. Man, Y. Liu, C. Feng, ... Leibo Liu*. “Mapzero: Mapping for coarse-grained reconfigurable architectures with reinforcement learning and monte-carlo tree search”. 2023 the 50th Annual International Symposium on Computer Architecture (ISCA), pp. 1-14.

12. Y. Wu, J. Zhu, W. Wei, L. Chen, L. Wang, S. Wei, Leibo Liu*. “Shogun: A Task Scheduling Framework for Graph Mining Accelerators.” 2023 the 50th Annual International Symposium on Computer Architecture (ISCA), pp. 1-14.

13. Yihong Zhu, Wenping Zhu, Min Zhu, Chongyang Li, Chenchen Deng, Chen Chen, Shuying Yin, Shouyi Yin, Shaojun Wei, Leibo Liu*. “A 28nm 48KOPS 3.4μJ/Op Agile Crypto-Processor for Post-Quantum Cryptography on Multi-Mathematical Problems”, 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA.

14. Huiyu Mo, Wenping Zhu, Wenjing Hu, Guangbin Wang, Qiang Li, Ang Li, Shouyi Yin, Shaojun Wei, Leibo Liu*. “A 28nm 12.1TOPS/W Dual-Mode CNN Processor Using Effective-Weight-Based Convolution and Error-Compensation-Based Prediction”, 2021 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA.

15. Jianfeng Zhu, Ao Luo, Guanhua Li, Bowei Zhang, Yong Wang, Gang Shan, Yi Li, Jianfeng Pan, Chenchen Deng, Shouyi Yin, Shaojun Wei, Leibo Liu*. “Jintide: Utilizing Low-Cost Reconfigurable External Monitors to Substantially Enhance Hardware Security of Large-Scale CPU Clusters”, IEEE Journal of Solid-State Circuits (JSSC), 56(8) (2021): 2585-2601.

16. Guiqiang Peng, Leibo Liu*, Sheng Zhou, Shouyi Yin, and Shaojun Wei. “A 2.92-Gb/s/W and 0.43-Gb/s/MG flexible and scalable CGRA-based baseband processor for massive MIMO detection”, IEEE Journal of Solid-State Circuits (JSSC), 55(2) (2020): 505-519.

17. N. Zhang, B. Yang, C. Chen, S. Yin, S. Wei, Leibo Liu*, “Highly Efficient Architecture of NewHope-NIST on FPGA using Low-Complexity NTT/INTT”, IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), Online, 14-17, September, 2020.

18. Z. Li, Leibo Liu*, Y. Deng, J. Wang, Z. Liu, S. Yin, S. Wei. “FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory”. In The 52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), October 12-16, 2019, Columbus, OH, USA. [Best Paper Nomination]

19. H. Mo, Leibo Liu*, W. Zhu, Q. Li, H. Liu, W. Hu, Y. Wang, S. Wei. “A 1.17 TOPS/W, 150fps Accelerator for Multi-Face Detection and Alignment”. 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC), Las Vegas, Nevada, USA, 2-7, June 2019, 1- 6, [Best Paper Nomination]

20. Leibo Liu, A. Luo, G. Li, J. Zhu, Y. Wang, G. Shan, J. Pan, S. Yin, S. Wei. “Jintide^®: A Hardware Security Enhanced Server CPU with Xeon^® Cores under Runtime Surveillance by an In-Package Dynamically Reconfigurable Computing Processor”. 31st Hot Chips: A Symposium on High Performance Chips (Hot Chips 2019), Stanford, Palo Alto, CA, USA, 18-20, August, 2019

21. Leibo Liu, J. Zhu, Z. Li, Y. Lu, Y. Deng, J. Han, S. Yin, S. Wei, “A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges and Applications”, ACM Computing Surveys (CSUR), 2019, 52(6): 1-39.

22. G. Peng, Leibo Liu*, Q. Wei, Y. Wang, S. Yin, S. Wei. “A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128*8 Massive MIMO Systems”, IEEE Asian Solid-State Circuits Conference (A-SSCC 2018), Tainan, Taiwan, 5-7 November.

23. Z. Li, Leibo Liu*, Y. Deng, S. Yin, Y. Wang, S. Wei, “Aggressive Parallelization of Irregular Applications on Reconfigurable Hardware”, the 44th International Symposium on Computer Architecture (ISCA), Toronto, Canada, June, 2017, pp. 575-586.DOI: 10.1145/3140659.3080228

24. Q. Wang, Leibo Liu*, W. Zhu, H. Mo, C. Deng, S. Wei, “A 700fps Optimized Coarse-to-Fine Shape Searching Based Hardware Accelerator for Face Alignment”, the 54th Annual Design Automation Conference (DAC 2017), Austin, TX, USA, June 2017, pp.57-57.DOI: 10.1145/3061639.3062182 [Best Paper Nomination].

25. B. Wang, Leibo Liu*, C. Deng, M. Zhu, S. Yin, Z. Zhou, S. Wei, “Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks”, IEEE Transactions on Information Forensics and Security (TIFS), vol. 12, no. 2, pp. 309-322, Feb. 2017. DOI: 10.1109/TIFS.2016.2612638.

26. S. Yin, P. Ouyang, S. Tang, F. Tu, X. Li, Leibo Liu, S. Wei. “High Energy-Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications”, the 23^rd International Symposium on Low Power Electronics and Design (ISLPED), Taipei, Taiwan, July, 2017 [Design Contest Award]

27. B. Wang, Leibo Liu*, C. Deng, M. Zhu, S. Yin, S. Wei, “Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture”, IEEE Transactions on Information Forensics and Security (TIFS), vol. 11, no. 6, pp. 1151-1164, 2016.

28. Leibo Liu, D. Wang, S. Yin, Y. Chen, M. Zhu, S. Wei, “SimRPU: A Simulation Environment for Reconfigurable Architecture Exploration,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 22, no. 12, pp. 2635-2648, 2014.

29. Leibo Liu, W. Zhu, S. Yin, E. Y. Tang, P. Peng, “An uneven-dual-core processor based mobile platform for facilitating the collaboration among various embedded electronic devices,” IEEE Transactions on Consumer Electronics (TCE), vol. 60, no. 1, pp. 137-145, 2014.

30. Leibo Liu, C. Deng, D. Wang, M. Zhu, S. Yin, P. Cao, S. Wei, “An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications,” the IEEE 2013 Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, Sep. 2013, pp. 1-4.

31. Leibo Liu, W. Zhang, C. Deng, S. Yin, “SURFEX. A 57fps 1080P resolution 220mW silicon implementation for simplified speeded-up robust feature with 65nm process,” the IEEE 2013 Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, Sep. 2013, pp. 1-4.

32. Leibo Liu, Meng H, Zhang L, et al. “An ASIC implementation of JPEG2000 codec,” the IEEE 2005 Custom Integrated Circuits Conference (CICC), 691-694.

33. Leibo Liu, N. Chen, H. Meng, L. Zhang, Z. Wang, H. Chen, “A VLSI architecture of JPEG2000 encoder,” IEEE Journal of Solid-State Circuits (JSSC), vol. 39, no. 11, pp. 2032-2040, Nov. 2004.