长聘副教授、博士生导师

电子邮箱：wdeng@tsinghua.edu.cn

电话:+86-10-62792712

地址：北京市清华大学自强科技楼2-512

邓伟，长聘副教授，博士生导师，入选国家高层次人才计划和国家青年人才计划。2002年-2009年在电子科技大学电子工程系先后获得学士和硕士学位；2009年-2014年在日本东京工业大学（Tokyo Institute of Technology）获得博士学位并从事博士后研究；2015年-2019年在美国苹果公司（Apple Inc.）总部任高级主任工程师，面向无线通信SoC和A系列处理器SoC从事射频、毫米波和混合信号芯片的研发。2019年起任职清华大学微纳电子系（现集成电路学院）。

邓伟副教授长期从事射频、毫米波和太赫兹芯片设计与系统集成，主持国家重点专项、基金委重点项目等一系列国家重点科技项目。现任ISSCC、VLSI、CICC、A-SSCC、RFIC和ESSCIRC的技术委员会成员，IEEE SSCS 杰出讲师（Distinguished Lecturer），以及IEEE JSSC、IEEE SSC-L、半导体学报等期刊副主编或客座编辑，负责射频和无线方向。在JSSC、IEEE T-MTT、IEEE T-CAS I等期刊以及ISSCC、VLSI等国际会议发表论文160余篇，其中在JSSC和ISSCC发表论文40余篇，申请和授权发明专利60余项。获得过IEEE SSCS Predoctoral Achievement Award、Tejima Research Award和IEEE/ACM ASP-DAC Best Design Award等奖项。相关研究应用于射频/毫米波无线通信、雷达和成像芯片系统。

讲授课程：电子电路与系统I（本科生）、集成电路课程设计（本科生）、模拟大规模集成电路B（研究生）

招生/招聘信息：本课题组每年招收4-5名博士和硕士研究生，常年招聘硅基混合信号、射频、毫米波和太赫兹芯片设计与系统集成等方向的博士后和工程师，同时也非常欢迎感兴趣的本科生参与科研。详情请附上简历咨询wdeng@tsinghua.edu.cn.

主要研究方向：

1. 硅基混合信号、射频、毫米波和太赫兹集成电路设计

2. 射频、毫米波和太赫兹收发芯片与微系统

主要编著：

[1] R. Wan, W. Deng, Q. Wu, H. Jia, R. Wu, A. Yan, H. Cai, S. Hu, Z. Wang, and B. Chi "A D-Band Distributed MIMO FMCW Radar CMOS Transceiver," in IEEE Journal of Solid-State Circuits (JSSC), doi: 10.1109/JSSC.2025.3579589

[2] J. Yin, W. Deng, H. Jia, S. Pan, M. Wang, T. Chen, H. Zhong, Z. Guo, Z. Wang, and B. Chi “A Time-Domain Accuracy Boosted Temperature Compensated Crystal Oscillator,” in IEEE Journal of Solid-State Circuits (JSSC). (Invited paper）

[3] Y. Yang, W. Deng, A. Yan, H. Jia, J. Gong, Z. Wang, and B. Chi"A Low-Spur and Low-Jitter Fractional Output Divider With Self-Adaption Frequency Filtering Technique," in IEEE Journal of Solid-State Circuits (JSSC), doi: 10.1109/JSSC.2025.3561203.

[4] R. Jiang, H. Jia, X. Huang, W. Deng, C. Zhu, X. Li, Z. Wang, and B. Chi, "A Ka-Band Multi-Beam Phased-Array Transmitter With Time-Modulation for PAPR Reduction and Physical Layer Security," IEEE Journal of Solid-State Circuits (JSSC), doi: 10.1109/JSSC.2025.3574578. (Invited paper）

[5] S. Zhang, W. Deng, H. Jia, Z. Wang, and B. Chi, “A Multi-Core Series-Resonance CMOS Oscillator,” in IEEE Journal of Solid-State Circuits (JSSC), vol. 60, no. 5, pp. 1644-1655, May 2025, doi: 10.1109/JSSC.2025.3529600 (Invited paper）

[6] A. Yan, W. Deng, H. Jia, Y. Yang, C. Tang, S. Sun, Z. Wang, and B. Chi, “An 11-to-16.4GHz, 3.4GHz/μs-Slope, 5.32GHz-Chirp-Bandwidth, 0.043%-RMS-Frequency-Error FMCW Digital PLL with Posterior-Segment DPD Featuring 5-Chirp-Cycle Convergence Time,” IEEE International Solid- State Circuits Conference (ISSCC), Feb. 2025.

[7] H. Liu, W. Deng, H. Jia, Z. Wang, and B. Chi, "An Ultra-Low-Jitter Fast-Hopping Fractional-N PLL With LC DTC and Hybrid-Proportional Paths," in IEEE Journal of Solid-State Circuits (JSSC), vol. 60, no. 3, pp. 785-798, March 2025, doi: 10.1109/JSSC.2024.3514870. (Invited paper）

[8] Q. Peng, H. Jia, R.Fang, P. Guan, M. Deng, J. Xue, W. Deng, X. Liang, B. Chi, "A 26-Gb/s 140-GHz OOK CMOS Transmitter and Receiver Chipset for High-Speed Wireless and Dielectric Waveguide Communication," in IEEE Journal of Solid-State Circuits (JSSC), vol. 60, no. 6, pp. 1985-1996, June 2025, doi: 10.1109/JSSC.2024.3483818.

[9] B. Zhu, W. Deng, Z. Huang, H. Jia, H. Jia, A. Yan, Y. Yang, J. Liu, Y. Fu, S. Sun, C. Tang, L. Kuang, L. Yu, Y. Liu, X. Liang, Z. Wang, and B. Chi, “A Digital-Intensive 1TX/2RX IEEE 802.15.4/4z- Compliant Joint-Radar-Communication-Location Transceiver SoC,” in IEEE Journal of Solid-State Circuits (JSSC), vol. 60, no. 3, pp. 1014-1029, March 2025, doi: 10.1109/JSSC.2024.3451654.

[10] P. Guan, R. Ma, H. Jia, W. Deng, M. Deng, J. Xue, A. Yan, S. Sun, Q. Peng, T. Siriburanon, R. Staszewski, Z. Wang, and B. Chi, "A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces," in IEEE Journal of Solid-State Circuits (JSSC), doi: 10.1109/JSSC.2024.3432759. Oct. 2024（Invited paper）

[11] S. Zhang, W. Deng, H. Jia, H. Liu, S. Sun, P. Guan, Z. Wang, and B Chi "A Transformer-Based Series-Resonance CMOS VCO," in IEEE Journal of Solid-State Circuits (JSSC), doi: 10.1109/JSSC.2024.3433521.

[12] X. Huang, H. Jia, W. Deng, Z. Wang and B. Chi, "A Compact E-Band Load-Modulation Balanced Power Amplifier in 65-nm CMOS," in IEEE Journal of Solid-State Circuits (JSSC), Oct. 2024 doi: 10.1109/JSSC.2024.3404610. （Invited paper）

[13] H. Liu, W. Deng, H. Jia, S. Zhang, S. Sun, Z. Wang, and B. Chi, “A Multi-Reference PLL: Theory and Implementation,” in IEEE Journal of Solid-State Circuits (JSSC), July 2024（Invited paper）

[14] Q. Wu, W. Deng, Y. Sun, H. Jia, H. Liu, S. Zhang, Z. Wang, and B. Chi, "An Enhanced Class-F Dual-Core VCO With Common-Mode-Noise Self-Cancellation and Isolation Technique," in IEEE Journal of Solid-State Circuits (JSSC), doi: 10.1109/JSSC.2024.3367351.

[15] F. Zhao, W. Deng, H. Jia, W. Ye, R. Wan, Z. Wang, and B. Chi “A Band-Shifting Millimeter-Wave T/R Front-End using Inductance-mutation Transformer Technique for Multi-band Phased-array Transceivers,” in IEEE Journal of Solid-State Circuits (JSSC) May 2024（Invited paper）

[16] H. Ge, H. Jia, W. Deng, R. Ma, Z. Wang, B. Chi, “A 13.7-to-41.5GHz 214.1dBc/Hz FoMT Quad-Core Quad-Mode VCO Using an Oscillation-Mode-Splitting Technique,” IEEE International Solid- State Circuits Conference (ISSCC), pp. 7-9, Feb. 2024

[17] Y. Sun, W. Deng, H. Jia, Y. He, Z. Wang and B. Chi, "A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique," in IEEE Journal of Solid-State Circuits (JSSC), doi: 10.1109/JSSC.2023.3266426. （Invited paper）

[18] Z. Lin, H. Jia, R. Ma, W. Deng, Z. Wang and B. Chi, "A Low-Phase-Noise VCO With Common-Mode Resonance Expansion and Intrinsic Differential 2nd-Harmonic Output Based on a Single Three-Coil Transformer," in IEEE Journal of Solid-State Circuits (JSSC), doi: 10.1109/JSSC.2023.3274178.

[19] Y. Yang, W. Deng, A. Yan, H. Jia, J. Gong, Z. Wang, and B. Chi, “A 10-to-300 MHz Fractional Output Divider with -80 dBc Worst-case Fractional Spurs using Auxiliary PLL based Background 0/1st/2nd-order DTC INL Calibration,” IEEE International Solid- State Circuits Conference (ISSCC), Feb. 2023, pp. 1-3, doi: 10.1109/ISSCC42615.2023.10067785.

[20] Q. Wu, W. Deng, H. Jia, H. Liu, S. Zhang, Z. Wang, B. Chi, “A 11.5-to-14.3 GHz 192.8-dBc/Hz FOM at 1MHz offset Dual-core Enhanced Class-F VCO with Common-mode Noise Self-cancellation and Isolation Technique,” IEEE International Solid- State Circuits Conference (ISSCC), pp. 7-9, Feb. 2023

[21] H. Jia, P. Guan, W. Deng, Z. Wang and B. Chi, "A Low-Phase-Noise Quad-Core Millimeter-Wave Fundamental VCO Using Circular Triple-Coupled Transformer in 65-nm CMOS," in IEEE Journal of Solid-State Circuits (JSSC), vol. 58, no. 2, pp. 371-385, Feb. 2023, doi: 10.1109/JSSC.2022.3196181.

[22] W. Deng, Z. Chen, H. Jia, P. Guan, T. Ma, S. Sun, X. Huang, G. Chen, R. Ma, S. Dong, L. Duan, Z. Wang, and B. Chi, “A D-band Joint Radar-Communication CMOS Transceiver,” IEEE Journal of Solid-State Circuits (JSSC), vol. 58, no. 2, pp. 411-427, Feb. 2023, doi: 10.1109/JSSC.2022.3185160.

[23] W. Deng, Z. Chen, H. Jia, S. Sun. G. Chen. Z. Wang, and B. Chi, "A Self-Adapted Two-Point Modulation Type-II Digital PLL for Fast Chirp Rate and Wide Chirp-Bandwidth FMCW Signal Generation," IEEE Journal of Solid-State Circuits (JSSC), vol. 57, no. 4, pp. 1162-1174, April 2022 （Invited paper）

[24] H. Jia, R. Ma, W. Deng, Z. Wang and B. Chi, "A 53.6-to-60.2GHz Many-Core Fundamental Oscillator with Scalable Mesh Topology Achieving -136.0dBc/Hz Phase Noise at 10MHz Offset and 190.3dBc/Hz Peak FoM in 65nm CMOS," IEEE International Solid- State Circuits Conference (ISSCC), pp. 154-156 Feb. 2022

[25] H. Jia, W. Deng, P. Guan, Z. Wang, and B. Chi,“A 60 GHz 186.5 dBc/Hz FOM Quad-Core Fundamental VCO using Circular-Triple-Coupled-Transformer with No Mode Ambiguity in 65nm CMOS,”   IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021.  

[26] W. Deng, Z. Song, R. Ma, J. Lin, J. Ye, S. Kong, S. Hu, H. Jia, and B. Chi, "An Energy-Efficient 10-Gb/s CMOS Millimeter-Wave Transceiver with Direct-Modulation Digital Transmitter and I/Q Phase-Coupled Frequency Synthesizer," IEEE Journal of Solid-State Circuits (JSSC), Vol. 55, No. 8, pp. 2027-2042, Aug. 2020

[27] T. Ma, W. Deng, Z. Chen, J. Wu, W. Zheng, S. Wang, N. Qi, Y. Liu, B. Chi, "A CMOS 76-81 GHz 2TX/3RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp Generator," IEEE Journal of Solid-State Circuits (JSSC), Vol. 55, No. 2, pp. 233-248, Feb. 2020

[28] H. Liu, Z. Sun, H. Huang, W. Deng, T.Siriburanon, J. Pang, Y.Wang, R.Wu, T.Someya, A.Shirane, and K.Okada, "A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Sub-sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS," IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 12, pp. 3478-3492, Dec. 2019. （Invited paper）

[29] H.Liu, Z. Sun, H. Huang, W. Deng, T.Siriburanon, J. Pang, Y.Wang, R.Wu, T.Someya, A.Shirane, and K.Okada, "A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2019.  （Invited to JSSC）

[30] H. Liu, D. Tang, Z. Sun, W. Deng, H. Ngo, and K. Okada, "A Sub-mW Fractional-N ADPLL with FOM of -246dB for IoT Applications," IEEE Journal of Solid-State Circuits (JSSC), Vol. 53, No. 12, Dec. 2018.  Invited paper）

[31] H. Liu, Z.Sun, D. Tang, H. Huang, T.Kaneko, Z. Chen, W. Deng, R. Wu and K. Okada,  "A DPLL-Centric Bluetooth Low-Energy Transceiver with a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65nm CMOS,"  IEEE Journal of Solid-State Circuits (JSSC), Vol. 53, No. 12, Dec. 2018. （Invited paper）

[32] H. Liu, D. Tang, Z. Sun, W. Deng, H. Ngo, K. Okada, and A. Matsuzawa, "A 0.98mW Fractional-N ADPLL Using 10b Isolated Constant-Slope DTC with FoM of -246dB for IoT Applications in 65nm CMOS," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2018. （Invited to JSSC）

[33] H. Liu, Z. Sun, D. Tang, H. Huang, T. Kaneko, W. Deng, R. Wu, K. Okada, and A. Matsuzawa, "An ADPLL-Centric Bluetooth Low-Energy Transceiver with 2.3mW Interference-Tolerant Hybrid-Loop Receiver and 2.9mW Single-Point Polar Transmitter in 65nm CMOS," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2018. （Invited to JSSC）

[34] A. Narayanan, M. Katsuragi, K. Kimura, S. Kondo, K.Tokgoz, K. Nakata, W. Deng, K. Okada, and A. Matsuzawa,  "A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with an FoM of -250dB," IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No. 7, pp. 1630-1640, Jul. 2016.（Invited paper）

[35] T. Siriburanon, S.Kondo, K. Kimura, T. Ueno, S. Kawashima, T. Kaneko, W. Deng, M. Miyahara, K. Okada, and A. Matsuzawa,  "A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using Digital Sub-Sampling Architecture,"  IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No.6 , pp. 1385-1397, Jun. 2016.

[36] T. Siriburanon, S. Kondo, M. Katsuragi, H. Liu, K. Kimura, W. Deng, K. Okada, and A. Matsuzawa, "A Low-Power Low-Noise mm-Wave Sub-Sampling PLL using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE802.11ad," IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No. 5, pp. 1246-1260, May 2016.

[37] W. Deng, D. Yang, A. Narayanan, K. Nakata, T. Siriburanon, K. Okada, and A. Matsuzawa, "A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 252-253, Feb. 2015.

[38] T. Siriburanon, S. Kondo, K. Kimura, T. Ueno, S. Kawashima, T. Kaneko, W.Deng, M. Miyahara, K. Okada, A. Matsuzawa,  "A 2.2-GHz -242dB-FoM 4.2-mW ADC-PLL Using Digital Sub-Sampling Architecture,"  IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 440-441, Feb. 2015.

[39] W. Deng, D. Yang, T. Ueno, T. Siriburanon, S. Kondo, K. Okada, and A. Matsuzawa, "A Fully Synthesizable All-Digital PLL with Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique," IEEE Journal of Solid-State Circuits (JSSC), Vol. 50, No. 1, pp. 68-80, Jan. 2015. （Invited paper）

[40] W. Deng, S. Hara, A. Musa, K. Okada, and A. Matsuzawa, "A Compact and Low-power Fractionally Injection-Locked Quadrature Frequency Synthesizer using Self-Synchronized Gating Injection Technique for Software-Defined Radios," IEEE Journal of Solid-State Circuits (JSSC), Vol. 49, No. 9, pp. 1984-1994, Sep. 2014.

[41] W. Deng, D. Yang, T. Ueno, T. Siriburanon, S. Kondo, K. Okada, and A. Matsuzawa, "A 0.0066mm2 780µW Fully Synthesizable PLL with a Current Output DAC and an Interpolative-Phase Coupled Oscillator using Edge Injection Technique," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp.266-267, Feb. 2014. （Invited to JSSC）

[42] A. Musa, W. Deng, T. Siriburanon, M. Miyahara, K.Okada, and A. Matsuzawa, "A Compact, Low Power and Low Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration," IEEE Journal of Solid-State Circuits (JSSC), Vol. 49, No. 1, pp. 50-60, Jan. 2014. （Invited paper）

[43] W. Deng, T. Siriburanon, A. Musa, K. Okada, and A. Matsuzawa, "A Sub-harmonic Injection-locked Quadrature Frequency Synthesizer with Frequency Calibration Scheme for Millimeter-wave TDD Transceivers," IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 7, pp. 1710-1720, Jul. 2013. （Invited paper）

[44] W. Deng, A. Musa, T. Siriburanon, M. Miyahara, K. Okada, and A. Matsuzawa, "A 0.022mm2 970µW Dual-loop Injection-Locked PLL with -243dB FOM using Synthesizable All-Digital PVT Calibration Circuits," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 248-249, Feb. 2013. （Invited to JSSC）

[45] W. Deng, K. Okada, and A. Matsuzawa, " Class-C VCO with Amplitude Feedback Loop for Robust Start-up and Enhanced Oscillation Swing",  IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 2, pp. 429-440, Feb. 2013.