LIU Xiaosen Associate Professor

Phone：+86-10-62771283

Email：liuxiaosen@tsinghua.edu.cn

Address：East Main Building 9-119, School of Integrated Circuits, Tsinghua University, Beijing, China, 100084

Prof. Xiaosen Liu is currently an Associate Professor in the School of Integrated Circuits at Tsinghua University. He was selected as a National-Level Leading Talent in Science and Technology Innovation in 2025 and a National High-Level Young Talent in 2020. He serves as Deputy Director of the Institute of Integrated Circuit Design and CAD.

He received the B.S. degree from the School of Electronic Science and Engineering, Southeast University, in 2008; the M.S. degree from the Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, in 2011 (advisor: Kevin J. Chen, IEEE Fellow); and the Ph.D. degree from the Department of Electrical and Computer Engineering, Texas A&M University, in 2016 (advisor: Edgar Sanchez-Sinencio, IEEE Life Fellow). From 2016 to 2022, he worked in the United States at the Circuit Research Lab within Intel Labs, successively serving as a Research Scientist, Senior Research Scientist, and Principal Research Scientist. In 2022, he joined the School of Integrated Circuits at Tsinghua University as an Associate Professor. His research interests include power integrated circuit design, power management systems, III-V power semiconductor circuits, and electronic design automation. His honors include the Chinese Government Award for Outstanding Self-Financed Students Abroad, the IEEE Solid-State Circuits Society (SSCS) Outstanding Ph.D. Award, and four Intel Labs Outstanding Contribution Awards.

As a technical lead, he led a digital/mixed-signal research team focused on power-management architectures for future chips, high-performance electronic design automation for advanced sub-10-nm processes, and integrated power architectures for hardware security. His work contributed to the development of key Intel products, including Intel Core^™ and Intel Xeon^® high-performance CPUs, PCH chipsets, XMM^™ 5G modems, and the x86/64 AES instruction set. His fully integrated voltage regulator (FIVR), digital linear voltage regulator (DLVR), and other mainstream power-delivery technologies have been deployed in the world's first commercial 2.5D/3D chiplet processor and have supported Turbo Boost and the Intel vPro^® hardware security platform. Under sponsorship from Medtronic, he investigated electrically powered medical devices and invented the architecture of the next-generation Sonicision^™ ultrasonic surgical dissector, for which he is the first-named inventor on the corresponding patent. He also contributed to the evolution of the Valleylab^™ electrosurgical platform. He proposed one of the earliest major architectures for IoT energy harvesting, which was adopted in Amazon AWS Industrial IoT and edge-computing solutions.

He has served as principal investigator or contributor on projects sponsored by the U.S. National Science Foundation, the U.S. Defense Advanced Research Projects Agency (DARPA), Intel, Covidien, and Texas Instruments. In recent years, he has led research projects funded by the National Key R&D Program of China (Young Scientist Project), the National Natural Science Foundation of China, and other programs. He has published more than 60 papers in leading conferences and journals, including ISSCC, IEDM, APEC, VLSI, JSSC, EDL, TED, TIE, and TCAD, and holds more than 30 U.S. patents, 11 of which have been granted. He serves on the technical committees of IEEE DAC, ISCAS, ISQED, and other international conferences. He is also a coordinator for the Semiconductor Research Corporation (SRC).

Group Openings: Our group has openings for 2-4 PhD/Master students every year and regularly recruit postdocs with related background in digital/mixed-signal IC design, power management and EDA. Undergraduate students are also encouraged to participate in our research. For more information, please email liuxiaosen@tsinghua.edu.cn with your CV.

Selected Publications

Patents

n U.S. Patent No. 010086217B2, “Electrosurgical Ultrasonic Vessel Sealing and Dissecting System,” X. Liu, A. I. Collie-Menchi, J. A. Gilbert, D. A. Friedrichs, K. W. Malan, and E. Sánchez-Sinencio, Covidien.

n U.S. Patent No. 20180284823A1, “Supply Generator with Programmable Power Supply Rejection Ratio,” X. Liu, T. Na, and H. K. Krishnamurthy, Intel Corporation.

n U.S. Patent No. US10530254B2, “Peak Delivered Power Circuit for a Voltage Regulator,” K. Ahmed, V. De, N. Desai, S. Kim, K. Krishnamurthy, X. Liu, T. Majumder, K. Ravichandran, C. Schaef, V. Vaidya, and S. Vangal, Intel.

n U.S. Patent No. 20190006939A1, “Master-Slave Controller Architecture Technical Field,” H. Krishnamurthy, K. Ahmed, V. De, N. Desai, S. Kim, X. Liu, T. Majumder, K. Ravichandran, C. Schaef, V. Vaidya, and S. Vangal, Intel Corporation.

n U.S. Patent No. US10958079B2, “Energy Harvester with Multiple-Input Multiple-Output Switched Capacitor (MIMOSC) Circuitry,” X. Liu, K. Ahmed, V. De, N. Desai, S. Kim, H. Krishnamurthy, T. Majumder, K. Ravichandran, C. Schaef, V. Vaidya, and S. Vangal, Intel.

n U.S. Patent No. 20210203228A1, “Non-Linear Clamp Strength Tuning Method and Apparatus,” X. Liu, H. Krishnamurthy, K. Ravichandran, and V. De, Intel.

n U.S. Patent No. US10845831B2, “Techniques in Hybrid Regulators of High Power Supply Rejection Ratio and Conversion Efficiency,” X. Liu, C. Barrera, H. Krishnamurthy, J. Han, K. Ravichandran, R. Narayana Bhatla, S. Chiu, and V. De, Intel Corporation.

n U.S. Patent No. 010474174B2, “Programmable Supply Generator,” T. Na, H. K. Krishnamurthy, and X. Liu, Intel.

n U.S. Patent No. US10897364B2, “Physically Unclonable Function Implemented with Spin Orbit Coupling Based Magnetic Memory,” V. De, K. Ravichandran, H. Krishnamurthy, K. Ahmed, S. Vangal, V. Vaidya, T. Majumder, C. Schaef, S. Kim, X. Liu, and N. Desai, Intel.

n U.S. Patent No. 20190094931A1, “Energy Harvesting Source and Ambient Condition Tracking in IoT for Adaptive Sensing and Self-modifying Application Code,” K. Ahmed, V. De, N. Desai, S. Kim, H. Krishnamurthy, X. Liu , T. Majumder, K. Ravichandran, C. Schaef, V. Vaidya, and S. Vangal, Intel.

n U.S. Patent No. US20200350817A1, “Multiple Output Voltage Conversion,” V. De, K. Ravichandran, H. Krishnamurthy, K. Ahmed, S. Vangal, V. Vaidya, T. Majumder, C. Schaef, S. Kim, X. Liu, and N. Desai, Intel.

Journals

n X. Wang, R. Chen, H. Wang, Y. Liu, W. Ki, Y. Wang, and X. Liu, "A 0.73 A/mm3 Switched-Capacitor-Stack-Inductor Volumetric Integrated Voltage Regulator With Auxiliary-Assisted Gain Boosting for High-Power-Density PoL Applications," IEEE Journal of Solid-State Circuits (JSSC), doi: 10.1109/JSSC.2026.3713507.H. Chang, J. Yang, J. Yu, Y. Lao, Y. Yin, H. Yang, X. Yang, J. Wang, X. Liu, M. Wang, B. Shen, and J. Wei, "High-Performance 1200-V p-GaN Gate HEMT on Standard 650-V GaN-on-Si Epi-Wafer," IEEE Transactions on Electron Devices (TED), vol. 73, no. 6, pp. 3360-3365, June 2026, doi: 10.1109/TED.2026.3664041

n C. Hu, X. Huang, X. Liu, S. Du, X. Liu and J. Jiang, “A 16 V-Output Switched-Capacitor Sigma Converter With 180 ns Transient Response and 94% Efficiency for LiDAR Receivers,” IEEE Journal of Solid-State Circuits (JSSC), doi: 10.1109/JSSC.2025.3645413.

n X. Liu, X. Sun, R. Chen, H. Zhang, Z. Liu and Y. Wang, “3D-IC Chiplet Integrated Power Supply With LDO, SCVR, and Buck DC–DC Converter,” IEEE Solid-State Circuits Letters (SSCL), vol. 8, pp. 341-344, 2025, doi: 10.1109/LSSC.2025.3624096.

n H. Chang, J. Yang, J. Yu, J. Cui, Y. Yin, X. Yang, X. Liu, M. Wang, B. Shen, and J. Wei, “900-V active-passivation p-GaN gate HEMT with suppressed floating Si substrate induced back-gating effect.” Appl. Phys. Lett. (APL), 21 April 2025; 126 (16): 163503. doi: 10.1063/5.0253093.

n Y. Yin, T. Li, J. Yang, J. Yu, Y. Lao, H. Chang, J. Duan, X. Liu, M. Wang, K. Tang, Y. Cai, B. Shen, and J. Wei, “Demonstration of One Transistor - One Diode (1T1D) p-GaN/AlGaN/GaN Memory Cell,” IEEE Electron Device Letters (EDL), doi: 10.1109/LED.2025.3581752.

n J. Yang, J. Yu, J. Cui, S. Liu, T. Li, Y. Lao, H. Chang, M. Wang, J. Wang, X. Liu, J. Wei, and B. Shen, “Charge Balance Design of 1200-V E-mode p-GaN Gate HEMT towards Enhanced Breakdown Voltage and Dynamic Stability,” IEEE Electron Device Letters (EDL), 2025.

n X. Liu, J. Yu, M. Gong, N. Butzen, S. Weng, H. K. Krishnamurthy, K. Ravichandran, R. H. Ahangharnejhad, W. James, P. Christopher, J. W. Tschanz, and V. De, “A Monolithic 5.7 A/mm2 91% Peak Efficiency Scalable Multistage Modular Switched Capacitor Voltage Regulator for Base Die Vertical Power Delivery in 3D-ICs,” IEEE Journal of Solid-State Circuits (JSSC), 2025.

n S. Kim, H. K. Krishnamurthy, Z. K. Ahmed, N. Desai, S. Weng, A. E. Augustine, H. T. Do, J. Yu, P. D. Bach, X. Liu, K. Radhakrishnan, K. Ravichandran, J. W. Tschanz, and V. De, “A Monolithic, 10.5 W/mm2, 600 MHz Top-Metal and C4 Planar Spiral Inductor-Based Integrated Buck Voltage Regulator on 16 nm Class,” IEEE Journal of Solid-State Circuits (JSSC), vol. 60, no. 1, pp. 75-84, Jan. 2025.

n J. Cui, J. Yang, J. Yu, T. Li, H. Yang, X. Liu, J. Wang, M. Wang, B. Shen, and J. Wei; “GaN-on-sapphire JTE-anode lateral field-effect rectifier for improved breakdown voltage (>2.5 kV) and dynamic RON,” Applied Physics Letters (APL), 21 October 2024; 125 (17): 173503.

n J. Yang, M. Wang, J. Yu, Y. Wu, J. Cui, T. Li, H. Yang, J. Wang, X. Liu, X. Yang, B. Shen, and J. Wei, "Virtual-Body p-GaN Gate HEMT With Enhanced Ruggedness Against Hot-Electron-Induced Degradation," IEEE Electron Device Letters (EDL), vol. 45, no. 5, pp. 770-773, May 2024.

n J. Cui, Y. Wu, J. Yang, J. Yu, T. Li, X. Liu, K. Cheng, X. Yang, Y. Hao, J. Wang, B. Shen, M Wang, and J. Wei, "High-Voltage E-Mode p-GaN Gate HEMT on Sapphire With Gate Termination Extension," IEEE Transactions on Electron Devices (TED), vol. 71, no. 3, pp. 1592-1597, March 2024.

n J. Yang, J. Wei, Y. Wu, J. Yu, J. Cui, X. Yang, X. Liu, J. Wang, Y. Hao, M. Wang, and B Shen, “Enhanced robustness against hot-electron-induced degradation in active-passivation p-GaN gate HEMT,” Applied Physics Letters (APL), 4 March 2024; 124 (10): 103505.

n Y. Wu, M. Nuo, J. Yang, W. Lin, X. Liu, X. Yang, J. Wang, Y. Hao, B. Shen, M. Wang, and J. Wei, “Suppression of Buffer Trapping Effect in GaN-on-Si Active-Passivation p-GaN Gate HEMT via Light/Hole Pumping,” IEEE Transactions on Electron Devices (TED), vol. 71, no. 1, pp. 484-489, Jan. 2024.

n J. Cui, M. Wang, Y. Wu, J. Yang, H. Yang, J. Yu, T. Li, X. Yang, X. Liu, K. Cheng, J. Wang, B. Shen, and J. Wei, “Demonstration of 1200-V E-Mode GaN-on-Sapphire Power Transistor With Low Dynamic ON-Resistance Based on Active Passivation Technique,” IEEE Electron Device Letters (EDL), vol. 45, no. 2, pp. 220-223, Feb. 2024.

n X. Wang, X. Liu and W. -H. Ki, "A Self-Clocked and Variation-Tolerant Unified Voltage-and-Frequency Regulator for In-Order Executed Digital Loads," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 70, no. 11, pp. 4627-4640, Nov. 2023.

n X. Liu, S. Yaldiz, P. Mukherjee, S. Burns, H. Krishnamurthy, K. Ravichandran, Z. Ahmed, N. Desai, N. Butzen, J. Tschanz, and Vivek De, “A Digital LDO in 22-nm CMOS With a 4-b Self-Triggered Binary Search Windowed Flash ADC Featuring Analog Layout Generator Framework,” IEEE Solid-State Circuits Letters (SSCL), vol. 6, pp. 101-104, 2023.

n S. Yin, R. Wang, J. Zhang, X. Liu and Y. Wang, “Fast Surrogate-assisted Constrained Multi-objective Optimization for Analog Circuit Sizing via Self-adaptive Incremental Learning,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 42, no. 7, pp. 2080-2093, July 2023.

n D. Das, M. Nath, B. Chatterjee, R. Kumar, X. Liu, H. Krishnamurthy, M. Sastry, S. Mathew, S. Ghosh, and S. Sen, “EM SCA White-box Analysis Based Reduced Leakage Cell Design and Pre-Silicon Evaluation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 41, no. 11, pp. 4927-4938, Nov. 2022.

n X. Liu, H. K. Krishnamurthy, T. Na, S. Weng, Z. Ahmed, K. Ravichandran, J. Tschanz, and V. De, “A Universal Modular Hybrid LDO with Fast Load Transient Response and Programmable PSRR in 14-nm CMOS Featuring Dynamic Clamp Strength Tuning,” IEEE Journal of Solid-State Circuits (JSSC), invited, vol. 56, no. 8, pp. 2402-2415, Aug. 2021.

n J. Silva-Martinez, X. Liu and D. Zhou, “Recent Advances on Linear Low-Dropout Regulators,” IEEE Transactions on Circuits and Systems II: Express Briefs, invited tutorial, vol. 68, no. 2, pp. 568-573, Feb. 2021.

n R. Kumar, X. Liu, V. Suresh, H. K. Krishnamurthy, S. Satpathy, M. Anders, K. Himanshu, K. Ravichandran, V. De, and S. K. Mathew, “A Time/Frequency-domain Side-channel Attach Resistant AES-128 and RSA-4K Crypto-Processor in 14nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC), invited, vol. 56, no. 4, pp. 1141-1151, Apr. 2021.

n X. Liu, H. K. Krishnamurthy, C. Barrera, J. Han, R. M. Narayana Bhatla, S. Chiu, Z. K. Ahmed, N. Desai, K. Ravichandran, J. W. Tschanz, V. De, “A Dual-Rail Hybrid Analog/Digital Low Dropout Regulator with Dynamic Current Steering for a Tunable High PSRR and High Efficiency,” IEEE Solid-State Circuits Letters, invited, vol. 3, pp. 526-529, 2020.

n Z. Ahmed, H. Krishnamurthy, C. Augustine, X. Liu, W. Sheldon, K. Ravichandran, J. Tschanz, and V. De, “A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response,” IEEE Journal of Solid-State Circuits (JSSC), invited, vol. 55, no. 4, pp. 977-987, Apr. 2020.

n C. Schaef, D. Nachiket, K. Harish, X. Liu, Z. Ahmed, K. Suhwan, W. Sheldon, H. Do, W. Lambert, K. Ravichandran, K. Radhakrishnan, J. Tschanz, and V. De, “A Light-Load Efficient Fully Integrated Voltage Regulator in 14 nm CMOS with 2.5 nH Package-Embedded Air-Core Inductors,” IEEE Journal of Solid-State Circuits (JSSC), invited, vol. 54, no. 12, pp. 3316-3325, Dec. 2019.

n X. Liu, K. Ravichandran and E. Sánchez-Sinencio, “A Switched Capacitor Energy Harvester Based on a Single-Cycle Criterion for MPPT to Eliminate Storage Capacitor,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 2, pp. 793-803, Feb. 2018.

n H. Krishnamurthy, V. Vaidya, P. Kumar, R. Jain, S. Weng, S. Kim, G. Matthew, N. Desai, X. Liu, K. Ravichandran, J. Tschanz, and V. De, “A Digitally Controlled Fully Integrated Voltage Regulator with On-Die Solenoid Inductor with Planar Magnetic Core in 14nm Tri-Gate CMOS,” IEEE Journal of Solid-State Circuits (JSSC), invited, vol. 53, no. 1, pp. 8-19, Jan. 2018.

n Q. Zhou, Y. Shi, C. Dong, L. Zhu, D. Wei, X. Liu, W. Chen, and B. Zhang, “A Lateral AlGaN/GaN Diode with MIS-Gated Hybrid Anode for Ultra-Low Turn-On and High Breakdown Voltage,” ECS Journal of Solid State Science and Technology. 2017 6(11): S3056-S3059.

n X. Liu, A. Colli-Menchi, and E. Sanchez-Sinencio, “Ultrasonic Electric Scalpels Based on a Sliding-Mode Controller With an Auxiliary PLL Frequency Discriminator,” IEEE Transaction on Biomedical Circuits and Systems (BioCAS), invited, vol. 11, no. 6, pp. 1226-1235, Dec. 2017.

n X. Liu, L. Huang, K. Ravichandran, and E. Sanchez-Sinencio, “A Highly Efficient Reconfigurable Charge Pump Energy Harvester with Wide Harvesting Range and Two-Dimensional MPPT for Internet of Things,” IEEE Journal of Solid-State Circuits (JSSC), vol. 51, no. 5, pp. 1302-1312, May 2016.

n X. Liu and E. Sanchez-Sinencio, “An 86% Efficiency 12 μW Self-sustaining PV Energy Harvesting System with Hysteresis Regulation and Time-domain MPPT for IOT Smart Nodes,” IEEE Journal of Solid-State Circuits (JSSC), vol. 50, no. 6, pp. 1424-1437, Mar. 2015.

n X. Liu, A. Colli-Menchi, J. Gilbert, D. Friedrichs, K. Malang, and E. Sanchez-Sinencio, “An Automatic Resonance Tracking Scheme With Maximum Power Transfer for Piezoelectric Transducers,” IEEE Transactions on Industrial Electronics (TIE), vol.62, no.11, pp.7136-7145, Nov. 2015.

n X. Liu and E. Sanchez-Sinencio, “A Highly-Efficient Ultra-Low Photovoltaic Power Harvesting System with MPPT for Internet of Things (IOT) Smart Nodes,” IEEE Transactions on VLSI Systems, vol. 23, no. 12, pp. 3065-3075, Dec. 2015.

n A.M.H. Kwan, G. Yue, X. Liu, K.J. Chen, “A Highly Linear Integrated Temperature Sensor on a GaN Smart Power IC Platform,” IEEE Transactions on Electron Devices (TED), vol. 61, no. 8, pp. 2970-2976, Aug. 2014.

n X. Liu, K. J. Chen, “GaN Single-Polarity Power Supply Bootstrapped Comparator for High Temperature Electronics,” IEEE Electron Device Letters (EDL), vol. 32, No. 1, pp. 27-29, Jan. 2011.

n A. M. H. Kwan, K. -Y. Wong, X. Liu, and K. J. Chen, “High-gain and high-bandwidth AlGaN/GaN high electron mobility transistor comparator with high-temperature operation,” Japanese Journal of Applied Physics, vol 50, No. 4, 2011.

n K. -Y. Wong, W. Chen, X. Liu, C. Zhou, and K. J. Chen “GaN Smart Power IC Technology,” Physica Status Solidi, 247, No. 7, pp. 1732-1734, 2010.

n X. Liu, N. Wu, S. Chen “Interactive Simulation of Solid Physics Model Structure with OpenGL,” Chinese Journal of Electron Devices, Vol.30 No.5 P.1926-1929, 2007.

Conference Proceedings

n J. Yang, J. Yu, H. Chang, Y. Lao, J. Cui, H. Yang, X. Yang, X. Liu, M. Wang, B. Shen, and J. Wei, "6.5 kV Enhancement-Mode GaN Monolithic Bidirectional Switch (MBDS) Achieving Record Power Figure of Merit," IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI), Honolulu, HI, USA, 2026, pp. 1-3, doi: 10.1109/VLSITechnologyandCir65830.2026.11577570.

n R. Chen, Z. Liu, X. Men, X. Wang, Y. Wang and X. Liu, "A Triple-Path Resonant-Tracked Voltage Regulator with Package Inductor for System-on-Wafer Vertical Power Delivery," IEEE 38th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Las Vegas, NV, USA, 2026, pp. 93-96, doi: 10.1109/ISPSD64561.2026.11553581.

n Y. Liu, R. Yue, X. Liu and Y. Wang, "SiC MOSFET with Two Embedded Series-Opposed Polysilicon Diodes for Improved Short-Circuit Capability," IEEE 38th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Las Vegas, NV, USA, 2026, pp. 429-432, doi: 10.1109/ISPSD64561.2026.11553964.

n J. Yang, J. Yu, J. Cui, S. Liu, H. Chang, H. Yang, X. Yang, X. Liu, M. Wang, B. Shen, and J. Wei, "6.2 kV/12.4 mΩ•cm2 Superjunction GaN Lateral Field-Effect Rectifier with Low Dynamic ON-Resistance," IEEE 38th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Las Vegas, NV, USA, 2026, pp. 45-48, doi: 10.1109/ISPSD64561.2026.11553625.

n X. Tang, S. Yin, Z. Yao, B. Huang, X. Liu and Y. Wang, "RASNIL: PVT-Robust Many-Objective Analog Sizing via Nested Hybrid Fidelity Framework with Incremental Learning," Design, Automation & Test in Europe Conference (DATE), Verona, Italy, 2026, pp. 1-7, doi: 10.23919/DATE69613.2026.11539738.

n H. Wang, Z. Liu, J. Xu, X. Wang, M. Xiong, Y. Liu, X. Li, J. Cui, Y. Wang, and X. Liu, “A 1295W/in3 160A Quad-Phase VPD Module with Flexible Ganging and Multiphysics Optimization for Large-Scale HPC Systems,” 2026 IEEE Applied Power Electronics Conference and Exposition (APEC), San Antonio, TX, USA, 2026, pp. 1060-1066, doi: 10.1109/APEC51134.2026.11517052.

n H. Wang, Z. Liu, J. Xu, X. Wang, M. Xiong, Y. Liu, X. Li, J. Cui, Y. Wang, and X. Liu, “Current–Temperature–Resistance Modeling and Conversion Loss Sharing Methodology for Optimized Efficiency and Thermal Distribution in Large-Scale HPC Power Delivery Networks,” 2026 IEEE Applied Power Electronics Conference and Exposition (APEC), San Antonio, TX, USA, 2026, pp. 1216-1221, doi: 10.1109/APEC51134.2026.11517022.

n H. Wang, Z. Liu, J. Xu, X. Wang, M. Xiong, Y. Liu, X. Li, J. Cui, Y. Wang, and X. Liu, “A 30-60V Input 6V Output Regulated Resonant SC Converter with Unified Hard-Soft Switching Control Achieving 100A and 1339W/in3 for High-Performance Computing,” 2026 IEEE Applied Power Electronics Conference and Exposition (APEC), San Antonio, TX, USA, 2026, pp. 1693-1699, doi: 10.1109/APEC51134.2026.11516838.

n X. Wang, H. Wang, Z. Liu, Y. Yao, Y. Liu, W. H. Ki, J. Wei, Y. Wang, and X. Liu, “A Multi-Resonant Cascaded Series-Parallel Switched-Capacitor Converter Featuring Continuously Scalable Conversion Ratio,” 2026 IEEE Applied Power Electronics Conference and Exposition (APEC), San Antonio, TX, USA, 2026, pp. 2097-2103, doi: 10.1109/APEC51134.2026.11516812 .

n X. Wang, H. Wang, Z. Liu, Y. Yao, Y. Liu, W. H. Ki, J. Wei, Y. Wang, and X. Liu, “X-ReLA: a Family of Stacked-Ladder Charge-Cross-Converging ReSC with 98.2% Peak Efficiency Featuring Wide Voltage Conversion Ratio and Always Reduced Inductor Current,” 2026 IEEE Applied Power Electronics Conference and Exposition (APEC), San Antonio, TX, USA, 2026, pp. 3314-3320, doi: 10.1109/APEC51134.2026.11516977.

n X. Wang, H. Wang, X. Men, R. Chen, J. Jiang, Y. Wang, and X. Liu, “Unicorn: A Unified Clock-and-Power SoC with RL-Adapted Digital SIMO Control and In-TRO Frequency Boosting for Edge Computing,” IEEE Custom Integrated Circuits Conference (CICC), Boston, MA, USA, 2025, pp. 1-8, doi: 10.1109/CICC63670.2025.10982997.

n Y. Liu, J. Zhang, X. Liu, and Y. Wang, “A 14GHz Chopper-Refolding Sampling PLL Achieving 33.8fsrms and 80.8dBc Reference Spur with a kT/C-Noise-Cancellation SPD,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2026.

n P. An, G. Yang, G. Chai, Z. Liu, J. Cui, S. Liu, J. Wei, B. Shen, Y. Wang, and X. Liu, “Monolithic BEOL-Compatible Multi-Layer High-Density MIM Capacitor for Power Integrity Optimization and Vertical Power Delivery in HPC 3D ICs,” IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2025, pp. 1-4.

n Y. Fan, J. Tang, Y. Su, H. Zhou, R. Chen, X. Liu, H. Zhang, K. Wang, Z. Tang, Y. Zhang, J. Li, J. Li, L. Wang, Y. Du, P. Yao, B. Gao, H. Qian, and H. Wu, “High-Performance IGZO-based DrMOS with Vertical Channel Power Transistor for Monolithic 3D Integrated Active PDNs with On-Chip Voltage Conversion,” IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2025, pp. 1-4.

n X. Tang, W. Hu, Z. Wang, X. Liu and Y. Wang, “Fast Yield Analysis and Optimization Based on Sensitivity and Orthogonal Sampling,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), doi: 10.1109/TCAD.2025.3586887.

n X. Sun, X. Wang, R. Chen, X. Men, J. Jiang, Y. Wang, and X. Liu, “A 10W 3.8-5V Input IVR Chiplet with 93%-Peak-Efficiency and 3.2A/mm2 Density Featuring Wide Load Range and Adaptive Ganging for 2.5D/3D Vertical Power Delivery,” 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2025, pp. 1-3, doi: 10.23919/VLSITechnologyandCir65189.2025.11074928.

n J. Yang, S. Liu, J. Yu, J. Cui, H. Chang, T. Li, Y. Lao, X. Yang, X. Liu, M. Wang, B. Shen, and J. Wei, “3-KV GaN Smart Power Integration Platform for High-Power-Density Conversion Systems Using Charge-Balanced Superjunction Technology,” 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2025, pp. 1-3, doi: 10.23919/VLSITechnologyandCir65189.2025.11074938.

n H. Wang, X. Wang, Y. Wang and X. Liu, “Evaluation Index-Based Multiphysics Coupling Model and Analysis Methodology for High-Reliable Power Supply Module,” 2025 IEEE Applied Power Electronics Conference and Exposition (APEC), Atlanta, GA, USA, 2025, pp. 2556-2561, doi: 10.1109/APEC48143.2025.10977494.

n H. Wang, X. Wang, Y. Wang and X. Liu, “A 660W, 96% Efficiency 3D Heterogeneously Integrated Digital DC/DC Power Module for Vertical Power Delivery,” 2025 IEEE Applied Power Electronics Conference and Exposition (APEC), Atlanta, GA, USA, 2025, pp. 1544-1550, doi: 10.1109/APEC48143.2025.10977479.

n X. Wang, H. Wang, Y. Liu, Y. Wang, B. Zhang, H. Liu, Y. Wang, X. Liu, “Concurrent Charge Distribution and Time-Optimal Control for Unordered Single-Inductor Dual-Output Converter,” 2025 IEEE Applied Power Electronics Conference and Exposition (APEC), Atlanta, GA, USA, 2025, pp. 2675-2680, doi: 10.1109/APEC48143.2025.10977130.

n J. Yu, J. Yang, J. Cui, H. Chang, S. Liu, Y. Lao, X. Yang, X. Liu, M. Wang, B. Shen, and J. Wei, "9-kV p-GaN Gate HEMT with Gate Termination Extension Demonstrated on Sapphire Substrate for Improved Breakdown Voltage," 2025 9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Hong Kong, Hong Kong, 2025, pp. 1-3, doi: 10.1109/EDTM61175.2025.11040986.

n X. Liu, X. Sun, H. Zhang and Y. Wang, "3D-IC Chiplet Integrated Power Supply with LDO, SCVR, and Buck DC-DC Converter," IEEE Custom Integrated Circuits Conference (CICC), Boston, MA, USA, 2025, pp. 1-8, doi: 10.1109/CICC63670.2025.10982997.

n L. Zhu, C. Hu, W. -H. Ki, X. Liu, X. Liu and J. Jiang, "A 6.87W 3.7-5V Input 12.6-24V Output Switched-Capacitor Sigma Converter with Multiple Voltage Domains," IEEE Custom Integrated Circuits Conference (CICC), Boston, MA, USA, 2025, pp. 1-3, doi: 10.1109/CICC63670.2025.10983553.

n J. Yang, J. Yu, J. Cui, S. Liu, H. Chang, Y. Lao, H. Yang, T. Li, X. Yang, J. Wang, X. Liu, Y. Wang, M. Wang, B. Shen, and J. Wei, “10-kV E-mode GaN Lateral Superjunction Transistor,” IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2024, pp. 1-4.

n Y. Shi, C. Hu, X. Liu, X. Liu and J. Jiang, “Methods of Reducing the Intrinsic Loss for Continuously-Scalable-Conversion-Ratio SC Converters,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Taipei, Taiwan, 2024, pp. 763-766.

n J. Yu, X. Liu, M. Gong, N. Butzen, S. Weng, H. K Krishnamurthy, K. Ravichandran, R. H Ahangharnejhad, W. Jim, P. Christopher, J. W Tschanz, and Vivek De, “A Monolithic 5.7A/mm2 91% Peak Efficiency Scalable Multi-Stage Modular Switched Capacitor Voltage Regulator with Self-Timed Deadtime and Safe Startup for 3D-ICs,” IEEE Symposia on VLSI Technology & Circuits (VLSI), Jun. 2024.

n J. Yang, J. Yu, J. Cui, T. Li, Y. Lao, X. Yang, B. Shen, X. Liu, Y. Wang, M. Zhang, M. Wang, and J. Wei, “Metal/Insulator/p-GaN Gate Virtual-Body HEMT for Large Gate Swing and Effective hole Injection,” International Symposium on Power Semiconductor Devices and ICs (ISPSD), Bremen, Germany, 2024, pp. 287-290,

n Z. Wang, Z. Ye, J. Zhou, X. Liu, and Y. Wang, “A Two-step Fine-tuning Assisted Layout Sizing Scheme for Analog/RF Circuits,” IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, 2024, pp. 1-5,

n X. Sun, J. Yu, X. Wang, J. Wei, J. Jiang, C. Zhan, Yan Wang, and X. Liu, “A 92%-Efficiency 0.828μs Settling Time FC5L Voltage Regulator Featuring Time-Domain Charge Balancing & Flying Capacitor Self-Switching for Wide Dynamic Range & Fast Transient Chiplet Applications,” IEEE Custom Integrated Circuits Conference (CICC), Denver, CO, USA, 2024, pp. 1-2.

n Z. Wang, J. Zhou, X. Liu and Y. Wang, "An Efficient Transfer Learning Assisted Global Optimization Scheme for Analog/RF Circuits," Asia and South Pacific Design Automation Conference (ASP-DAC), Incheon, Korea, Republic of, 2024, pp. 417-422.

n C. Hu, X. Huang, X. Liu, S. Du, X. Liu and J. Jiang, “31.7 A 3.6W 16V-Output 180ns-Response-Time 94%-Efficiency SC Sigma Converter with Output Impedance Compensation and Ripple Mitigation for LiDAR Driver Applications,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024, pp. 508-510.

n S. Kim, H. K Krishnamurthy, Z. Ahmed, N. Desai, S. Weng, A. Augustine, H. T. Do, J. Yu, P. D. Bach, X. Liu, K. Radhakrishnan, K. Ravichandran, J. W. Tschanz, and V. De, “14.9 A Monolithic 10.5W/mm2600 MHz Top-Metal and C4 Planar Spiral Inductor-Based Integrated Buck Voltage Regulator on 16nm-Class CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024, pp. 270-272.

n J. Cui, J. Wei, M. Wang, Y. Wu, J. Yang, T. Li, J. Yu, H. Yang, X. Yang, J. Wang, X. Liu, D. Ueda, and B Shen, “6500-V E-mode Active-Passivation p-GaN Gate HEMT with Ultralow Dynamic RON,” International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2023, pp. 1-4.

n X. Liu, S. Yaldiz, P. Mukherjee, S. Burns, H. Krishnamurthy, K. Ravichandran, Z. Ahmed, N. Desai, N. Butzen, J. Tschanz, and V. De, “A Digital LDO in 22nm CMOS with a 4b Self-triggered Binary Search Windowed Flash ADC Featuring Automatic Analog Layout Generator Framework,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Taipei, Taiwan, 2022, pp. 2-4.

n H. Wang, R. Liu, R. Dorrance, D. Dasalukunte, X. Liu, D. Lake, B. Carlton, M. Wu, "A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference," IEEE Symposium on VLSI Technology and Circuits (VLSI), Honolulu, HI, USA, 2022, pp. 36-37.

n X. Liu, H. Krishnamurthy, R. Liu, K. Ravichandran, Z. Ahmed, N. Desai, N. Butzen, J. Tschanz, and V. De, “A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise Analyzer,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 478-479, Feb. 2022.

n Z. Ahmed, N. Desai, H. Krishnamurthy, S. Weng, X. Liu, K. Ravichandran, J. Tschanz, and V. De, “A Dual-Input, Digital Hybrid Buck-LDO System Featuring Fast Load Transient Response, Zero-Wire Current Handover & Input PDN Resonance Reduction,” IEEE Symposia on VLSI Technology & Circuits (VLSI), Jun. 2021.

n N. Desai, H. Krishnamurthy, Z. Ahmed, S. Weng, S. Kim, X. Liu, H. Do, K. Radhakrishnan, K. Ravichandran, J. Tschanz, V. De, “Peak-Current-Controlled Ganged Integrated High-Frequency Buck Voltage Regulators in 22nm CMOS for Robust Cross-Tile Current Sharing,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 262-263, Feb. 2021.

n X. Liu, H. Krishnamurthy, C. Barrera, J. Han, R. Narayana Bhatla, S. Chiu, Z. Ahmed, K. Ravichandran, J. Tschanz, and V. De, “A Dual-Rail Hybrid Analog/Digital LDO with Dynamic Current Steering for Tunable High PSRR & High Efficiency,” IEEE Symposia on VLSI Technology & Circuits (VLSI), Jun. 2020.

n R. Kumar, X. Liu, V. Suresh, H. Krishnamurthy, M. Anders, H. Kaul, K. Ravichandran, V. De, and S. Mathew, “A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-linear Digital LDO Cascaded with Arithmetic Countermeasures,” IEEE Symposia on VLSI Technology & Circuits (VLSI), Jun. 2020.

n Z. Ahmed, H. Krishnamurthy, S. Weng, X. Liu, C. Schaef, N. Desai, K. Ravichandran, J. Tschanz, and V. De, “An Autonomous Reconfigurable Power Delivery Network (RPDN) for Many-Core SoCs Featuring Dynamic Current Steering,” IEEE Symposia on VLSI Technology & Circuits (VLSI), Jun. 2020.

n H. Krishnamurthy, Z. Ahmed, X. Liu, N. Desai, S. Kim, N. Butzen, S. Amin, S. Weng, K. Ravichandran, J. Tschanz, and V. De, “Digital Control of Switching and Linear Integrated Voltage Regulators,” IEEE Custom Integrated Circuits Conference (CICC), invited talk.

n Z. Ahmed, H. Krishnamurthy, C. Augustine, X. Liu, S. Weng, K. Ravichandran, J. Tschanz, and V. De, “A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response,” IEEE Symposia on VLSI Technology & Circuits (VLSI), pp. 124-125, Jun. 2019.

n X. Liu, H. K Krishnamurthy, T. Na, S. Weng, K. Z Ahmed, K. Ravichandran, J. Tschanz, V. De, “A Modular Hybrid LDO with Fast Load-Transient Response and Programmable PSRR in 14nm CMOS Featuring Dynamic Clamp Tuning and Time-Constant Compensation,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 234-235, Feb. 2019.

n S. Kim, V. Vaidya, C. Schaef, A. Lines, H. Krishnamurthy, S. Weng, X. Liu, D. Kurian, T. Karnik,K. Ravichandran, J. Tschanz, and V. De, “A Single-Stage, Single-Inductor, 6 Input 9 Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120mW Battery Powered IoT Edge Nodes,” IEEE Symposia on VLSI Technology and Circuits (VLSI), pp. 195-196, Jun. 2018.

n X. Liu, A. Colli-Menchi, and E. Sanchez-Sinencio, “21.4 A Reduced-Order Sliding-Mode Controller with an Auxiliary PLL Frequency Discriminator for Ultrasonic Electric Scalpels,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 358-359, Feb. 2017.

n X. Liu, A. Colli-Menchi, and E. Sanchez-Sinencio, Student Research Preview, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2016.

n X. Liu and E. Sanchez-Sinencio, “21.1 A Single-cycle MPPT Charge Pump Energy Harvester using a Thyristor-based VCO without Storage Capacitor,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 364-365, Feb. 2016.

n X. Liu and E. Sanchez-Sinencio, “A 0.45-to-3V Reconfigurable Charge-Pump Energy Harvester with Two-Dimensional MPPT for Internet of Things,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 370-371, Feb. 2015.

n J. Amanor-Boadu, M.A. Abouzied, S. Carreon-Bautista, R. Ribeiro, X. Liu, E. Sanchez-Sinencio, “A switched mode Li-ion battery charger with multiple energy harvesting systems simultaneously used as input sources,” IEEE 57th International Midwest Symposium on Circuits and Systems, pp. 330-333, Aug. 2014.

n L. Ibarra, B. Hilton, M. Nawal, S. Carreon-Bautista, M. Abouzied, X. Liu, R. Ribeiro, J. Amanor-Badu, E. Miller, J. Vanegas, E. Sanchez-Sinencio, “SmartShelter: A Sustainable power system design using energy harvesting techniques,” IEEE 57th International Midwest Symposium on Circuits and Systems, pp. 467-470, Aug. 2014.

n H. Zhang, X. Liu, M. Kedia, R. Balog, “Photovoltaic Hybrid Power Harvesting System for Emergency Applications,” IEEE Photovoltaic Specialists Conference, 2013.

n A. M. H. Kwan, X. Liu, and K. J. Chen, “Integrated gate-protected HEMTs and mixed-signal functional blocks for GaN smart power ICs,” IEEE International Electron Devices Meeting (IEDM), pp.7.3.1-4, Dec. 2012.

n X. Liu, K. J. Chen, “Single-Polarity Power Supply Bootstrapped Comparator for GaN Smart Power Technology,” IEEE Compound Semiconductor IC Symposium, Monterey CA, Oct 3-6, 2010.

n A. M. H. Kwan, K. –Y. Wong, X. Liu, and K. J. Chen, “High-Gain and High-Bandwidth AlGaN/GaN HEMT Comparator,” International Conference on Solid State Devices and Materials, Tokyo, Japan, Sep. 22-24, 2010.

n K. J. Chen, K. -Y. Wong, W. J. Chen, C. Zhou, and X. Liu, (Invited) “Device Technology Platform for GaN Smart Power ICs,” International Electron Device and Material Symposium, Taoyuan, Taiwan, Nov. 18-21, 2009.

n K. -Y. Wong, W. J. Chen, X. Liu, C. Zhou, and K. J. Chen, “GaN Smart Power IC Technology,” 8th International Conference on Nitride Semiconductors, Jeju, Korea, Oct. 18-23, 2009.